Received: with ECARTIS (v1.0.0; list netdev); Tue, 22 Mar 2005 12:53:47 -0800 (PST) Received: from parcelfarce.linux.theplanet.co.uk (IDENT:93@parcelfarce.linux.theplanet.co.uk [195.92.249.252]) by oss.sgi.com (8.13.0/8.13.0) with ESMTP id j2MKrgx5002623 for ; Tue, 22 Mar 2005 12:53:42 -0800 Received: from cpe-069-134-152-124.nc.rr.com ([69.134.152.124] helo=[10.10.10.88]) by parcelfarce.linux.theplanet.co.uk with asmtp (TLSv1:AES256-SHA:256) (Exim 4.33) id 1DDqNh-0001GD-DG; Tue, 22 Mar 2005 20:53:41 +0000 Message-ID: <424085C9.3020608@pobox.com> Date: Tue, 22 Mar 2005 15:53:29 -0500 From: Jeff Garzik User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.7.3) Gecko/20040922 X-Accept-Language: en-us, en MIME-Version: 1.0 To: Michael Chan CC: "David S. Miller" , netdev@oss.sgi.com Subject: Re: [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt References: In-Reply-To: Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-Virus-Scanned: ClamAV 0.83/778/Mon Mar 21 02:48:43 2005 on oss.sgi.com X-Virus-Status: Clean X-archive-position: 481 X-ecartis-version: Ecartis v1.0.0 Sender: netdev-bounce@oss.sgi.com Errors-to: netdev-bounce@oss.sgi.com X-original-sender: jgarzik@pobox.com Precedence: bulk X-list: netdev Content-Length: 393 Lines: 10 Michael Chan wrote: > Add register read of PCI state register in tg3_interrupt() if status block's > updated bit is not set. This will flush the status block and confirm whether > the interrupt is ours or not. PCI ordering rules allow the interrupt to > arrive at the CPU ahead of the status block that may be posted at the > chipset. > > Signed-off-by: Michael Chan